Redmine: Issueshttps://redmine.libresilicon.com/https://redmine.libresilicon.com/favicon.ico?16780521372023-02-28T13:16:36ZRedmine
Redmine LibrePDK - Fehler #11 (Neu): nplus/pplus for resistorshttps://redmine.libresilicon.com/issues/112023-02-28T13:16:36ZPhilipp Gühring
<p>resistors on ndiffusion/pdiffusion need a nplus/pplus area with overhang undeneath, according to gf180mcuC</p> Danube River - Fehler #10 (In Bearbeitung): Capacitance test structures documentationhttps://redmine.libresilicon.com/issues/102023-01-07T18:05:06ZPhilipp Gühring
<p>The documentation for Capacitace tests just says "The target value of this capacitor is"</p> Danube River - Feature #9 (In Bearbeitung): CSV outputhttps://redmine.libresilicon.com/issues/92023-01-07T18:02:28ZPhilipp Gühring
<p>DanubeRiver should generate a CSV file (perhaps by being given a file-path parameter "-csv filename.csv" ) which should contain a table of all the test-structures with the following fields:</p>
<ul>
<li>Which GDS file was it placed on (in case we have multiple GDS files)</li>
<li>Test-Pattern ID</li>
<li>X/Y coordinates of the test-structure on the die (could be split up into 2 fields)</li>
<li>ID for the pin-pattern (usually "4" for the 4-ping configuration, could be also just "2" if just 2 pins are used, or "4-2" if 4 pins are there but only 2 of them are used, ...</li>
<li>Kind of test (resistance, transistor, ...)</li>
<li>Test setup/input parameters</li>
<li>Expected results</li>
<li>Primary layer of the test-structure</li>
<li>Other comments about the test</li>
</ul> Libre Silicon Compiler - Feature #7 (Neu): Global Routinghttps://redmine.libresilicon.com/issues/72019-07-07T14:29:26ZAndreas Westerwickandreas.westerwick@libresilicon.com
<p><a class="external" href="https://doi.org/10.1016/0167-9260(92)90010-v">https://doi.org/10.1016/0167-9260(92)90010-v</a></p> Libre Silicon Compiler - Feature #6 (Neu): Compiler Pass: Verify DRChttps://redmine.libresilicon.com/issues/62019-07-07T14:24:09ZAndreas Westerwickandreas.westerwick@libresilicon.com
<p>Verify design rule constraints by means of symbolic execution.</p> Libre Silicon Compiler - Feature #5 (Neu): Nature of Single-Segment Clusteringhttps://redmine.libresilicon.com/issues/52019-07-07T14:09:59ZAndreas Westerwickandreas.westerwick@libresilicon.com
<p>Leaving out SSC in the FastDP detailed placement algorithm makes it matrix-based as opposed to cartesian.</p>
<pre><code>- Will the sum of all HPWL improve after applying FastDP w/o SSC?<br /> - Will it improve significantly by applying SSC?</code></pre> Libre Silicon Compiler - Feature #4 (Neu): Design Constraints before Synthesishttps://redmine.libresilicon.com/issues/42019-07-07T14:05:44ZAndreas Westerwickandreas.westerwick@libresilicon.com
<p>Like <a class="issue tracker-2 status-1 priority-2 priority-default" title="Feature: Design Constraints after Synthesis (Neu)" href="https://redmine.libresilicon.com/issues/3">#3</a> but it should work before synthesis.</p>
<p>When optimizations are made that rewrite logic gates and therefore signals, one of the following holds:</p>
<pre><code>- The compiler attempts to rewrite the constraint and prints a warning<br /> - The compiler errors out when the optimization cannot be applied</code></pre>
<p>By disabling optimizations during synthesis (-O0), no design constraint will make the compiler error out.</p> Libre Silicon Compiler - Feature #3 (Neu): Design Constraints after Synthesishttps://redmine.libresilicon.com/issues/32019-07-07T14:00:06ZAndreas Westerwickandreas.westerwick@libresilicon.com
<p>For synthesized netlists also offer design rule contraints for nets in those netlists.</p> Pearl River - Fehler #2 (Neu): Contacts have the wrong sizehttps://redmine.libresilicon.com/issues/22019-07-06T14:20:02ZDavid Lanzendörfer
<p>The contact holes in the LTO do not all have the same dimensions.<br />This violates the design rules.<br />All holes should be at least 2x2 lambda, or better even 4x4 lambda</p>