Redmine

The LibreSilicon PDK

The CMOS implementation of the cult timer chip 555 using the LibrePDK NMOS/PMOS

The collaborative effort to have the best formulation possible of our free silicon license

The Pad Cells for the one micron LibreSilicon node

The LibreSilicon web presence

Our fork of Magic with modifications to the technology

The manufacturing process for building the LibrePDK/PearlRiver

A RISC-V based simplistic micro controller unit synthesized using the one micron LibrePDK

The test wafer for the LibrePDK

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.

A fully integrated EDA for VLSI design using Qt5

The Sau Mau Ping SoC is based on Rocket Chip and contains a multi core RISC-V CPU
which is being untethered from FPGA-infrastructure so that it can be built bare metal.

In addition effort is being done to replace the Rocket Chip AXI bus for periphery interconnection...

Test ground for manually designed test logic structures