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  • Danube River

    A test wafer generator, written in Python, which generates test structures for characterizing new processes, using parameters defined in a configuration file.

  • LibrePDK

    The LibreSilicon PDK

  • LS556

    The CMOS implementation of the cult timer chip 555 using the LibrePDK NMOS/PMOS

  • Libre Silicon Public License

    The collaborative effort to have the best formulation possible of our free silicon license

  • LibreSilicon 1 micron (LS1U) PadCells

    The Pad Cells for the one micron LibreSilicon node

  • LibreSilicon Statutes

    These are the statutes of the LibreSilicon foundation.

  • LibreSilicon website

    The LibreSilicon web presence

  • Magic

    Our fork of Magic with modifications to the technology

  • Manufacturing Process

    The manufacturing process for building the LibrePDK/PearlRiver

  • Maskless lithography

    A collection of ideas, brain storming, drawings and so on, in order to build a machine which
    doesn't require physical mask sets and can project the layouts onto the wafer on its own.

  • Mini Clean Room Glove Box

    This project aims a mini clean room environment using the glove box approach in order to allow you building microchips in your garage.

  • North Point

    A RISC-V based simplistic micro controller unit synthesized using the one micron LibrePDK

  • Pad Cell Generator

    The goal of this project is to dynamically generate pad cells using the LibrePDK, so that LibreSilicon pad frames can be generated based on individual varying design rules.

  • Pearl River

    The test wafer for the LibrePDK

  • PicoRV32 - A Size-Optimized RISC-V CPU

    PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.

  • Pure Digital

    A purely digital System On Chip

  • QtFlow

    A fully integrated EDA for VLSI design using Qt5

  • Sau Mau Ping SoC

    The Sau Mau Ping SoC is based on Rocket Chip and contains a multi core RISC-V CPU
    which is being untethered from FPGA-infrastructure so that it can be built bare metal.

    In addition effort is being done to replace the Rocket Chip AXI bus for periphery interconnection...

  • Standard Cell Lib

    Test ground for manually designed test logic structures

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