General

Profile

Andreas Westerwick

Issues

open closed Total
Assigned issues 5 0 5
Reported issues 5 0 5

Projects

Project Roles Registered on
Libre Silicon Compiler Manager, Entwickler, Reporter 06/16/2019
arrowgant Manager 06/16/2019
blif Manager 06/16/2019
def Manager 06/16/2019
firrtl Manager 06/16/2019
lef Manager 06/16/2019
milp Manager 06/16/2019
verilog Manager 06/16/2019
LibrePDK Entwickler, Reporter 06/16/2019
LS556 Entwickler 06/16/2019
Libre Silicon Public License Manager, Entwickler 09/05/2019
LibreSilicon 1 micron (LS1U) PadCells Manager, Entwickler 10/13/2019
LibreSilicon website Manager, Entwickler 06/17/2019
North Point Manager, Entwickler 10/12/2019
Pearl River Entwickler 06/29/2019
PicoRV32 - A Size-Optimized RISC-V CPU Entwickler, Reporter 10/15/2019
Sau Mau Ping SoC Manager, Entwickler 09/07/2019

Activity

07/07/2019

02:29 PM Libre Silicon Compiler Feature #7 (Neu): Global Routing
https://doi.org/10.1016/0167-9260(92)90010-v Andreas Westerwick
02:24 PM Libre Silicon Compiler Feature #6 (Neu): Compiler Pass: Verify DRC
Verify design rule constraints by means of symbolic execution. Andreas Westerwick
02:09 PM Libre Silicon Compiler Feature #5 (Neu): Nature of Single-Segment Clustering
Leaving out SSC in the FastDP detailed placement algorithm makes it matrix-based as opposed to cartesian.
- Will...
Andreas Westerwick
02:05 PM Libre Silicon Compiler Feature #4 (Neu): Design Constraints before Synthesis
Like #3 but it should work before synthesis.
When optimizations are made that rewrite logic gates and therefore si...
Andreas Westerwick
02:00 PM Libre Silicon Compiler Feature #3 (Neu): Design Constraints after Synthesis
For synthesized netlists also offer design rule contraints for nets in those netlists. Andreas Westerwick

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