Project information

The Sau Mau Ping SoC is based on Rocket Chip and contains a multi core RISC-V CPU
which is being untethered from FPGA-infrastructure so that it can be built bare metal.

In addition effort is being done to replace the Rocket Chip AXI bus for periphery interconnection
with the TileLink bus, because AXI is under an ARM patent, which might cause legal issues
in the long run. TileLink is not patented however.

Time tracking

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